Merge branch 'tt10'

Author: rejunity

.devcontainer/Dockerfile

@@ -0,0 +1,27 @@
+ARG VARIANT=ubuntu-22.04
+FROM mcr.microsoft.com/vscode/devcontainers/base:${VARIANT}
+
+ENV DEBIAN_FRONTEND=noninteractive
+ENV PDK_ROOT=/home/vscode/ttsetup/pdk
+ENV PDK=sky130A
+
+RUN apt update
+RUN apt install -y iverilog gtkwave python3 python3-pip python3-venv python3-tk python-is-python3 libcairo2 verilator libpng-dev libqhull-dev
+
+# Clone tt-support-tools
+RUN mkdir -p /ttsetup
+RUN git clone -b tt10 https://github.com/TinyTapeout/tt-support-tools /ttsetup/tt-support-tools
+
+COPY test/requirements.txt /ttsetup/test_requirements.txt
+COPY .devcontainer/copy_tt_support_tools.sh /ttsetup
+
+RUN pip3 install -r /ttsetup/test_requirements.txt -r /ttsetup/tt-support-tools/requirements.txt
+
+# Install verible (for formatting)
+RUN umask 022 && \
+    curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3795-gf4d72375/verible-v0.0-3795-gf4d72375-linux-static-x86_64.tar.gz | \
+    tar zxf - -C /usr/local --strip-components=1 && \
+    chmod 755 /usr/local/bin
+
+# Install openlane
+RUN pip3 install openlane==2.1.5

.devcontainer/copy_tt_support_tools.sh

@@ -0,0 +1,6 @@
+#! /bin/sh
+
+if [ ! -L tt ]; then
+    cp -R /ttsetup/tt-support-tools tt
+    cd tt && git pull && cd ..
+fi

.devcontainer/devcontainer.json

@@ -0,0 +1,29 @@
+// For format details, see https://aka.ms/devcontainer.json. For config options, see the README at:
+// https://github.com/microsoft/vscode-dev-containers/tree/v0.183.0/containers/ubuntu
+{
+  "name": "Tiny Tapeout Dev Container",
+  "build": {
+    "dockerfile": "Dockerfile",
+    "context": ".."
+  },
+  "runArgs": [
+    "--memory=10GB"
+  ],
+  "customizations": {
+    "vscode": {
+      "settings": {
+        "terminal.integrated.defaultProfile.linux": "bash"
+      },
+      "extensions": ["mshr-h.veriloghdl", "surfer-project.surfer"]
+    }
+  },
+  "features": {
+    "ghcr.io/devcontainers/features/docker-in-docker:2": {
+      "moby": true,
+      "azureDnsAutoDetection": true,
+      "version": "latest",
+      "dockerDashComposeVersion": "none"
+    }
+  },
+  "postStartCommand": "/ttsetup/copy_tt_support_tools.sh"
+}

.github/workflows/docs.yaml

@@ -14,4 +14,4 @@ jobs:
           submodules: recursive
 
       - name: Build docs
-        uses: TinyTapeout/tt-gds-action/docs@tt09
+        uses: TinyTapeout/tt-gds-action/docs@tt10

.github/workflows/fpga.yaml

@@ -16,4 +16,4 @@ jobs:
           submodules: recursive
 
       - name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
-        uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt09
+        uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt10

.github/workflows/gds.yaml

@@ -14,7 +14,7 @@ jobs:
           submodules: recursive
 
       - name: Build GDS
-        uses: TinyTapeout/tt-gds-action@tt09
+        uses: TinyTapeout/tt-gds-action@tt10
         with:
           flow: openlane2
 
@@ -23,7 +23,7 @@ jobs:
     runs-on: ubuntu-24.04
     steps:
       - name: Run Tiny Tapeout Precheck
-        uses: TinyTapeout/tt-gds-action/precheck@tt09
+        uses: TinyTapeout/tt-gds-action/precheck@tt10
 
   gl_test:
     needs: gds
@@ -35,7 +35,7 @@ jobs:
           submodules: recursive
 
       - name: GL test
-        uses: TinyTapeout/tt-gds-action/gl_test@tt09
+        uses: TinyTapeout/tt-gds-action/gl_test@tt10
 
   viewer:
     needs: gds
@@ -44,4 +44,4 @@ jobs:
       pages: write      # to deploy to Pages
       id-token: write   # to verify the deployment originates from an appropriate source
     steps:
-      - uses: TinyTapeout/tt-gds-action/viewer@tt09
+      - uses: TinyTapeout/tt-gds-action/viewer@tt10

.vscode/extensions.json

@@ -0,0 +1,6 @@
+{
+  "recommendations": [
+    "mshr-h.veriloghdl",
+    "surfer-project.surfer"
+  ]
+}

.vscode/settings.json

@@ -0,0 +1,4 @@
+{
+  "verilog.linting.linter": "verilator",
+  "verilog.formatting.verilogHDL.formatter": "verible-verilog-format"
+}

src/config.json

@@ -60,15 +60,6 @@
 
   "FP_PDN_VPITCH": 38.87,
 
-  "//": "Use alternative efabless decap cells to solve LI density issue",
-  "DECAP_CELL": [
-    "sky130_fd_sc_hd__decap_3",
-    "sky130_fd_sc_hd__decap_4",
-    "sky130_fd_sc_hd__decap_6",
-    "sky130_fd_sc_hd__decap_8",
-    "sky130_ef_sc_hd__decap_12"
-  ],
-
   "//": "Clock",
   "RUN_CTS": 1,
 

src/tt_um_rejunity_z80.v

@@ -11,7 +11,7 @@ module tt_um_rejunity_z80 (
     input  wire [7:0] uio_in,   // IOs: Input path
     output wire [7:0] uio_out,  // IOs: Output path
     output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)
-    input  wire       ena,      // will go high when the design is enabled
+    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
     input  wire       clk,      // clock
     input  wire       rst_n     // reset_n - low to reset
 );